Scicos Hardware Description Language Tool (Version 0.5 released)

Scicos-HDL integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Scicos-HDL shortens digital circuit design cycles by helping you create the hardware representation in an modeling-friendly development environment. You can combine existing Scicos blocks with Scicos-HDL blocks and to link system-level design . It is a open source project under Scilab ‘s license, the release vision 0.5 can help to design and simulate some small-scale digital circuit system with its Hardware Description Language generation.Now it supports VHDL&Verilog Languages. URL:http://scicoshdl.sourceforge.net/

Scicos-HDL Features

• Links The Scilab/Scicos with the Digital circuit design(EDA).
• Integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation.
• Enables complex signal processing combined with powerful mathematical tools.
• Inside libraries: Sequential logic library, Combinational logic library, Ipcore library, simulation library.
• Support mixed-simulation with the Scicos blocks.
• Automatically generates a VHDL testbench.
• Automatically generates a Verilog testbench.
• Automatic propagation of signal names to generated HDL.
• Mix-simulation with original Scicos blocks and Scicos-HDL blocks.
• You can specify most values in the block parameter dialog boxes using Scicos workspace.
• Open interface for users to add blocks.
• Support: Windows XP, 2000, 98, Linux, UNIX, and Mac OS X.