library IEEE;
use ieee.std_logic_1164.ALL;
--  A testbench has no ports.
entity dclrtrig_tb is
end dclrtrig_tb;
 
architecture behav of dclrtrig_tb is
--  Declaration of the component that will be instantiated.
component dclrtrig
port(
NXUin_2_clk: in std_logic;
NXUin_3_clr: in std_logic;
NXUin_4_d: in std_logic;
NXUout_5_q: out std_logic);
end component;
--  Specifies which entity is bound with the component.
for dclrtrig_0: dclrtrig use entity work.dclrtrig;
signal tb_NXUin_1,tb_NXUin_2,tb_NXUin_3,NXUout_5_q: std_logic;
begin
--  Component instantiation.
dclrtrig_0: dclrtrig port map (NXUin_2_clk => tb_NXUin_1,NXUin_3_clr => tb_NXUin_2,NXUin_4_d => tb_NXUin_3,NXUout_5_q => NXUout_5_q);
 --  This process does the real job.
process
type pattern_type is record
--  The inputsThe expected outputs.
tb_NXUin_1,tb_NXUin_2,tb_NXUin_3: std_logic;
end record;
--  The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
begin
--  Check each pattern.
for i in patterns'range loop
--  Set the inputs.
tb_NXUin_1 <= patterns(i).tb_NXUin_1;
tb_NXUin_2 <= patterns(i).tb_NXUin_2;
tb_NXUin_3 <= patterns(i).tb_NXUin_3;
--  Wait for the results.
wait for 1 ns;
end loop;
wait;
end process;
end behav;
