
 library ieee;
 use ieee.std_logic_1164.ALL;
 use ieee.std_logic_arith.ALL;
 use ieee.std_logic_unsigned.ALL;

 entity muxBUS_3nxu is
  port(
      in_1 : in std_logic; --control

      in_2 : in std_logic; --indata high
      in_3 : in std_logic;
      in_4 : in std_logic;
      in_5 : in std_logic;

      in_6 : in std_logic; --indata low
      in_7 : in std_logic;
      in_8 : in std_logic;
      in_9 : in std_logic;
      in_10 : in std_logic;

      out_1 : out std_logic; --out1data high
      out_2 : out std_logic;
      out_3 : out std_logic;
      out_4 : out std_logic;

      out_5 : out std_logic;    
      out_6 : out std_logic;
      out_7 : out std_logic;
      out_8 : out std_logic;    

      out_9 : out std_logic; --out2data high
      out_10 : out std_logic;
      out_11 : out std_logic;
      out_12 : out std_logic;

      out_13 : out std_logic;    
      out_14 : out std_logic;
      out_15 : out std_logic;
      out_16 : out std_logic;   

      out_17 : out std_logic;          --out3 data high
      out_18 : out std_logic;
      out_19 : out std_logic;
      out_20 : out std_logic;

      out_21 : out std_logic;    
      out_22 : out std_logic;
      out_23 : out std_logic;
      out_24 : out std_logic
      );
 end muxBUS_3nxu;
  
 architecture one of muxBUS_3nxu is

 component muxBUS_3
  port( s1: in std_logic;
        s2: in std_logic;
        data : in std_logic_vector(7 downto 0);
          y1 : out std_logic_vector(7 downto 0);
          y2 : out std_logic_vector(7 downto 0);
          y3 : out std_logic_vector(7 downto 0));
 end component;
   
 signal nxu_in1 :  std_logic_vector(7 downto 0);  
 signal nxu_out1,nxu_out2 :  std_logic_vector(7 downto 0);
 signal nxu_out3 :  std_logic_vector(7 downto 0);     

begin

  nxu_in1 <= in_3&in_4&in_5&in_6&in_7&in_8&in_9&in_10;

  kczdmap: muxBUS_3 port map(s1=>in_1,s2=>in_2,data=>nxu_in1,
                     y1=>nxu_out1,y2=>nxu_out2,y3=>nxu_out3);
  
  out_1 <= nxu_out1(7);
  out_2 <= nxu_out1(6); 
  out_3 <= nxu_out1(5);
  out_4 <= nxu_out1(4);

  out_5 <= nxu_out1(3);
  out_6 <= nxu_out1(2); 
  out_7 <= nxu_out1(1);
  out_8 <= nxu_out1(0);

  out_9 <= nxu_out2(7);
  out_10 <= nxu_out2(6); 
  out_11 <= nxu_out2(5);
  out_12 <= nxu_out2(4);

  out_13 <= nxu_out2(3);
  out_14 <= nxu_out2(2); 
  out_15 <= nxu_out2(1);
  out_16 <= nxu_out2(0);

  out_17 <= nxu_out3(7);
  out_18 <= nxu_out3(6); 
  out_19 <= nxu_out3(5);
  out_20 <= nxu_out3(4);

  out_21 <= nxu_out3(3);
  out_22 <= nxu_out3(2); 
  out_23 <= nxu_out3(1);
  out_24 <= nxu_out3(0);

end;


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 --Copyright NXU AGL (2004-2007)
 
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