 
`include "D_trigger_3_1.v"
`timescale 1ns/1ns
module dclrtrig(NXUin_1_clk,NXUin_2_clr,NXUin_3_d,NXUout_1_q);
input NXUin_1_clk,NXUin_2_clr,NXUin_3_d;
output NXUout_1_q;
wire NXU_s3,NXU_s4,NXU_s5;
wire NXU_s9;
assign NXU_s3 = NXUin_1_clk;
assign NXU_s4 = NXUin_2_clr;
assign NXU_s5 = NXUin_3_d;
D_trigger_3_1 NXUmap1(.in_1(NXU_s3),.in_2(NXU_s4),
.in_3(NXU_s5),.out_1(NXU_s9));

assign NXUout_1_q = NXU_s9;
endmodule

