 
library IEEE;
use ieee.std_logic_1164.ALL;
entity fulladder is
port(
NXUin_12_CI: in std_logic;
NXUin_13_B: in std_logic;
NXUin_14_A: in std_logic;
NXUout_15_CO: out std_logic;
NXUout_16_SUM: out std_logic);
end fulladder;
architecture NXU_beh of fulladder is
component andgate2_2_1
port(
in_1,in_2: in std_logic;
out_1: out std_logic);
end component;
component andgate3_3_1
port(
in_1,in_2,in_3: in std_logic;
out_1: out std_logic);
end component;
component notgate_1_1
port(
in_1: in std_logic;
out_1: out std_logic);
end component;
component norgate4_4_1
port(
in_1,in_2,in_3,in_4: in std_logic;
out_1: out std_logic);
end component;
component norgate3_3_1
port(
in_1,in_2,in_3: in std_logic;
out_1: out std_logic);
end component;
component SPLIT_f_ZK_1_4
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4: out std_logic);
end component;
component SPLIT_f_ZK_1_3
port(
in_1: in std_logic;
out_1,out_2,out_3: out std_logic);
end component;
signal NXU_s15,NXU_s11: std_logic;
signal NXU_s12,NXU_s1: std_logic;
signal NXU_s16,NXU_s2: std_logic;
signal NXU_s9,NXU_s13,NXU_s20: std_logic;
signal NXU_s17,NXU_s6,NXU_s21: std_logic;
signal NXU_s18,NXU_s14,NXU_s3: std_logic;
signal NXU_s8: std_logic;
signal NXU_s5: std_logic;
signal NXU_s10,NXU_s7,NXU_s4: std_logic;
signal NXU_s26,NXU_s27,NXU_s28,NXU_s29: std_logic;
signal NXU_s22,NXU_s23,NXU_s24: std_logic;
signal NXU_s19: std_logic;
signal NXU_s41: std_logic;
signal NXU_s42: std_logic;
signal NXU_s43: std_logic;
signal NXU_s44: std_logic;
signal NXU_s45: std_logic;
signal NXU_s46: std_logic;
signal NXU_s25: std_logic;
signal NXU_s30: std_logic;
begin
NXU_s43<=NXUin_12_CI;
NXU_s42<=NXUin_13_B;
NXU_s46<=NXUin_14_A;
NXUmap1: andgate2_2_1 port map(in_1 => NXU_s15,in_2 => NXU_s11,out_1 => NXU_s22);
NXUmap2: andgate2_2_1 port map(in_1 => NXU_s12,in_2 => NXU_s1,out_1 => NXU_s23);
NXUmap3: andgate2_2_1 port map(in_1 => NXU_s16,in_2 => NXU_s2,out_1 => NXU_s24);
NXUmap4: andgate3_3_1 port map(in_1 => NXU_s9,in_2 => NXU_s13,in_3 => NXU_s20,out_1 => NXU_s26);
NXUmap5: andgate3_3_1 port map(in_1 => NXU_s17,in_2 => NXU_s6,in_3 => NXU_s21,out_1 => NXU_s27);
NXUmap6: andgate3_3_1 port map(in_1 => NXU_s18,in_2 => NXU_s14,in_3 => NXU_s3,out_1 => NXU_s28);
NXUmap7: notgate_1_1 port map(in_1 => NXU_s8,out_1 => NXU_s45);
NXUmap8: notgate_1_1 port map(in_1 => NXU_s5,out_1 => NXU_s44);
NXUmap9: andgate3_3_1 port map(in_1 => NXU_s10,in_2 => NXU_s7,in_3 => NXU_s4,out_1 => NXU_s29);
NXUmap10: norgate4_4_1 port map(in_1 => NXU_s26,in_2 => NXU_s27,in_3 => NXU_s28,in_4 => NXU_s29,out_1 => NXU_s30);
NXUmap11: norgate3_3_1 port map(in_1 => NXU_s22,in_2 => NXU_s23,in_3 => NXU_s24,out_1 => NXU_s25);
NXUmap12: notgate_1_1 port map(in_1 => NXU_s19,out_1 => NXU_s41);
NXUmap13: SPLIT_f_ZK_1_4 port map(in_1 => NXU_s41,out_1 => NXU_s1,out_2 => NXU_s2,out_3 => NXU_s3,out_4 => NXU_s4);
NXUmap14: SPLIT_f_ZK_1_3 port map(in_1 => NXU_s42,out_1 => NXU_s5,out_2 => NXU_s6,out_3 => NXU_s7);
NXUmap15: SPLIT_f_ZK_1_3 port map(in_1 => NXU_s43,out_1 => NXU_s8,out_2 => NXU_s9,out_3 => NXU_s10);
NXUmap16: SPLIT_f_ZK_1_4 port map(in_1 => NXU_s44,out_1 => NXU_s11,out_2 => NXU_s12,out_3 => NXU_s13,out_4 => NXU_s14);
NXUmap17: SPLIT_f_ZK_1_4 port map(in_1 => NXU_s45,out_1 => NXU_s15,out_2 => NXU_s16,out_3 => NXU_s17,out_4 => NXU_s18);
NXUmap18: SPLIT_f_ZK_1_3 port map(in_1 => NXU_s46,out_1 => NXU_s19,out_2 => NXU_s20,out_3 => NXU_s21);
NXUout_15_CO<=NXU_s25;
NXUout_16_SUM<=NXU_s30;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
