
 library ieee;
 use ieee.std_logic_1164.ALL;
 use ieee.std_logic_arith.ALL;
 use ieee.std_logic_unsigned.ALL;

 entity demuxBUS_3nxu is
  port(
      in_1 : in std_logic; --control
      in_2 : in std_logic;         

      in_3 : in std_logic;--in1 data high
      in_4 : in std_logic;
      in_5 : in std_logic;
      in_6 : in std_logic;          

      in_7 : in std_logic; --in1 data low
      in_8 : in std_logic;
      in_9 : in std_logic;          
      in_10 : in std_logic;

      in_11 : in std_logic;
      in_12 : in std_logic;
      in_13 : in std_logic;   
      in_14 : in std_logic;

      in_15 : in std_logic;
      in_16 : in std_logic;   
      in_17 : in std_logic;        
      in_18 : in std_logic;

      in_19 : in std_logic;
      in_20 : in std_logic;
      in_21 : in std_logic;    
      in_22 : in std_logic;

      in_23 : in std_logic;
      in_24 : in std_logic;   
      in_25 : in std_logic;
      in_26 : in std_logic; 

      out_1 : out std_logic;--out1 data high
      out_2 : out std_logic;
      out_3 : out std_logic;
      out_4 : out std_logic;

      out_5 : out std_logic;   
      out_6 : out std_logic;
      out_7 : out std_logic;
      out_8 : out std_logic);
 end demuxBUS_3nxu;
  
 architecture one of demuxBUS_3nxu is

 component demuxBUS_3
  port( s1: in std_logic;
        s2: in std_logic;
        data1 : in std_logic_vector(7 downto 0);
        data2 : in std_logic_vector(7 downto 0);
        data3 : in std_logic_vector(7 downto 0);
           y1 : out std_logic_vector(7 downto 0));
 end component;
   
   signal nxu_in1,nxu_in2,nxu_in3  :  std_logic_vector(7 downto 0);  
   signal nxu_out1:  std_logic_vector(7 downto 0);     


begin

 nxu_in1 <= in_3&in_4&in_5&in_6&in_7&in_8&in_9&in_10;
 nxu_in2 <= in_11&in_12&in_13&in_14&in_15&in_16&in_17&in_18;
 nxu_in3 <= in_19&in_20&in_21&in_22&in_23&in_24&in_25&in_26;

 kczdmap: demuxBUS_3 port map(s1=>in_1,s2=>in_2,data1=>nxu_in1,
                   data2=>nxu_in2,data3=>nxu_in3,y1=>nxu_out1);
  
 out_1 <= nxu_out1(7);
 out_2 <= nxu_out1(6); 
 out_3 <= nxu_out1(5);
 out_4 <= nxu_out1(4);

 out_5 <= nxu_out1(3);
 out_6 <= nxu_out1(2); 
 out_7 <= nxu_out1(1);
 out_8 <= nxu_out1(0);

end;


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