library ieee;
use ieee.std_logic_1164.all;
    
entity adder is
   -- i0, i1 and the carry-in ci are inputs of the adder.
   -- s is the sum output, co is the carry-out.
   port (in_1, in_2 : in std_logic; in_3 : in std_logic; out_1 : out std_logic; out_2 : out std_logic);
end adder;
     
architecture rtl of adder is
begin
    --  This full-adder architecture contains two concurrent assignment.
    --  Compute the sum.
    out_1 <= in_1 xor in_2 xor in_3;
       --  Compute the carry.
    out_2 <= (in_1 and in_2) or (in_1 and in_3) or (in_2 and in_3);
end rtl;
