
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity buma876 is 
 port( a: in std_logic_vector(7 downto 0);
       y: out std_logic_vector(7 downto 0));
end entity buma876;

architecture one of buma876 is
 begin

       y<=not a+'1';

end one;

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 --Copyright NXU AGL (2004-2007)
 
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