library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity parityCnxu is 
 
  port( in_1: in std_logic;
        in_2: in std_logic;
        in_3: in std_logic;
        in_4: in std_logic;
        in_5: in std_logic;
        in_6: in std_logic;
        in_7: in std_logic;
        in_8: in std_logic;
        in_9: in std_logic;
        in_10: in std_logic;
        --out1 data high
        out_1 : out std_logic;          
        out_2 : out std_logic
 
      );
end parityCnxu;
 
architecture one of parityCnxu is
  component parityC 
 
   port( pa_in,even_odd: in std_logic;
         data_in: in std_logic_vector(7 downto 0);
         pa_out,errork: out std_logic);
  end component;
 
  signal nxu_in1 :  std_logic_vector(7 downto 0);  
 
  begin
   nxu_in1 <= in_3&in_4&in_5&in_6&in_7&in_8&in_9&in_10;
 
   parityCmap: parityC port map(pa_in=>in_1,even_odd=>in_2,
             data_in=>nxu_in1,pa_out=>out_1,errork=>out_2);
  
end  one;
 
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 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
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