 module  muxkczd4(inputp,a,b,y);
 input a,b;
 input [3:0] inputp;     //input data 
 output y;
 reg y;
 reg [1:0] sel;
 
always@(a or b or inputp)
   begin
     sel={a,b};
   
    if (sel==2'b00) 
        y=inputp[0];
     else if (sel==2'b01) 
        y=inputp[1];
     else if (sel==2'b10) 
        y=inputp[2];
     else 
        y=inputp[3];
  end 

 endmodule
  
//******************************************************
 //Copyright NXU AGL (2004-2007)
 
 //Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 //http://scicoshdl.sourceforge.net
 
//******************************************************
