
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
 
entity parityC is 
  port(pa_in,even_odd: in std_logic;
       data_in: in std_logic_vector(7 downto 0);
       pa_out,errork: out std_logic);
end parityC;

architecture one of parityC is
  begin
    p1: process(pa_in,even_odd)
    begin
      if even_odd='1' then 
         pa_out<=data_in(7) xor data_in(6) xor data_in(5) xor data_in(4) 
             xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0);
         errork<=data_in(7) xor data_in(6) xor data_in(5) xor data_in(4) 
             xor data_in(3) xor data_in(2) xor data_in(1) xor data_in(0) 
             xor pa_in;
      else
        pa_out<=data_in(7) xnor data_in(6) xnor data_in(5) xnor data_in(4)
            xnor data_in(3) xnor data_in(2) xnor data_in(1) xnor data_in(0);
         errork<=data_in(7) xnor data_in(6) xnor data_in(5) xnor data_in(4)
            xnor data_in(3) xnor data_in(2) xnor data_in(1) xnor data_in(0) 
            xnor pa_in;
      end if;
    end process p1;
end one;
 
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