
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
 
entity hamgen is 
  port(data_in: in std_logic_vector(7 downto 0);
       ham_out: out std_logic_vector(3 downto 0));
end hamgen;

architecture one of hamgen is
  begin
 
    ham_out(3)<=data_in(7) xor data_in(6) xor data_in(4) xor
                data_in(3) xor data_in(1);
    ham_out(2)<=data_in(7) xor data_in(5) xor data_in(4) xor 
                data_in(2) xor data_in(1);
    ham_out(1)<=data_in(6) xor data_in(5) xor data_in(4) xor 
                data_in(0);
    ham_out(0)<=data_in(3) xor data_in(2) xor data_in(1) xor 
                data_in(0);
 end one;
 
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 --Copyright NXU AGL (2004-2007)
 
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 --http://scicoshdl.sourceforge.net
 
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