
library ieee;
use ieee.std_logic_1164.all;

entity half_adder is 
   port(in_1,in_2  : in std_logic;
        out_1,out_2 : out std_logic);
end entity half_adder;
architecture half of half_adder is
 signal c,d: std_logic;
 begin
   c<=in_1 or in_2;
   d<=in_1 nand in_2;
   out_2<= not d;
   out_1<=c and d;
end half;

--//u1=a ---u2=b  y1=s  y2=co

--******************************************************
  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

--******************************************************
