
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
 
entity muxBUS_2 is
  port(s1: in std_logic;
       data : in std_logic_vector(7 downto 0);
         y1 : out std_logic_vector(7 downto 0);
         y2 : out std_logic_vector(7 downto 0));
end muxBUS_2;

architecture mux2 of muxBUS_2 is

  begin
  p1:process(s1,data)
   begin
     if s1='1' then
        y1<=data;
        y2<="00000000";
     else
        y1<="00000000";
        y2<=data;
     end if;
  end process p1;
end mux2;
 
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