  
`define DELAY 1
module hamgen(data_in,ham_out);
 
input [7:0] data_in;     //input data
 
output [3:0] ham_out;   // delicate right or wrong
 
wire [7:0] data_in;     //input data
 
wire [3:0] ham_out;   // delicate right or wrong
 
parameter   DELAY=1;
 
assign #DELAY ham_out[3]=data_in[7] ^ data_in[6] ^ data_in[4] ^
                            data_in[3] ^ data_in[1];
assign #DELAY ham_out[2]=data_in[7] ^ data_in[5] ^ data_in[4] ^ 
                            data_in[2] ^ data_in[1];
assign #DELAY ham_out[1]=data_in[6] ^ data_in[5] ^ data_in[4] ^ 
                            data_in[0];
assign #DELAY ham_out[0]=data_in[3] ^ data_in[2] ^ data_in[1] ^ 
                            data_in[0];
  
endmodule
   

//******************************************************
 //Copyright NXU AGL (2004-2007)
 
 //Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 //http://scicoshdl.sourceforge.net
 
//******************************************************
