 
library IEEE;
use ieee.std_logic_1164.ALL;
entity SPLIT_f_ZK_1_7 is
port(
in_1: in std_logic;
out_1: out std_logic;
out_2: out std_logic;
out_3: out std_logic;
out_4: out std_logic;
out_5: out std_logic;
out_6: out std_logic;
out_7: out std_logic);
end SPLIT_f_ZK_1_7;
architecture NXU_beh of SPLIT_f_ZK_1_7 is
begin
p1: process(in_1)
variable indata: std_logic;
begin
indata := in_1;
case indata is
when '0' =>
out_1 <= '0';
out_2 <= '0';
out_3 <= '0';
out_4 <= '0';
out_5 <= '0';
out_6 <= '0';
out_7 <= '0';
when '1' =>
out_1 <= '1';
out_2 <= '1';
out_3 <= '1';
out_4 <= '1';
out_5 <= '1';
out_6 <= '1';
out_7 <= '1';
when others=>
out_1 <= '0';
out_2 <= '0';
out_3 <= '0';
out_4 <= '0';
out_5 <= '0';
out_6 <= '0';
out_7 <= '0';
end case;
end process p1;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
