 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity juedu79 is 
 port( a: in std_logic_vector(7 downto 0);
       y: out std_logic_vector(7 downto 0));
end entity juedu79;
architecture one of juedu79 is
 begin
  process(a)
   begin
   if a(7)<='0' then
       y<=a;
   else
       y(7)<='0';
       y(6)<=a(6);
       y(5)<=a(5);
       y(4)<=a(4);
       y(3)<=a(3);
       y(2)<=a(2);
       y(1)<=a(1);
       y(0)<=a(0);
  end if;
  end process;
end one;
 
  --  +127  -127
--******************************************************
 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
--******************************************************
