 
library IEEE;
use ieee.std_logic_1164.ALL;
entity encoderbtod is
port(
NXUin_19_A0: in std_logic;
NXUin_20_A1: in std_logic;
NXUin_21_A2: in std_logic;
NXUin_22_A3: in std_logic;
NXUout_23_Y_0: out std_logic;
NXUout_24_Y_1: out std_logic;
NXUout_25_Y_2: out std_logic;
NXUout_26_Y_3: out std_logic;
NXUout_27_Y_4: out std_logic;
NXUout_28_Y_5: out std_logic;
NXUout_29_Y_6: out std_logic;
NXUout_30_Y_7: out std_logic;
NXUout_31_Y_8: out std_logic;
NXUout_32_Y_9: out std_logic);
end encoderbtod;
architecture NXU_beh of encoderbtod is
component nandgate4_4_1
port(
in_1,in_2,in_3,in_4: in std_logic;
out_1: out std_logic);
end component;
component notgate_1_1
port(
in_1: in std_logic;
out_1: out std_logic);
end component;
component SPLIT_f_ZK_1_5
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4,out_5: out std_logic);
end component;
component SPLIT_f_ZK_1_7
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4,out_5,out_6,out_7: out std_logic);
end component;
component SPLIT_f_ZK_1_2
port(
in_1: in std_logic;
out_1,out_2: out std_logic);
end component;
component SPLIT_f_ZK_1_6
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4,out_5,out_6: out std_logic);
end component;
component SPLIT_f_ZK_1_9
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4,out_5,out_6,out_7,out_8,out_9: out std_logic);
end component;
component SPLIT_f_ZK_1_4
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4: out std_logic);
end component;
signal NXU_s23,NXU_s7,NXU_s14,NXU_s29: std_logic;
signal NXU_s1,NXU_s8,NXU_s15,NXU_s30: std_logic;
signal NXU_s24,NXU_s37,NXU_s16,NXU_s31: std_logic;
signal NXU_s2,NXU_s38,NXU_s17,NXU_s32: std_logic;
signal NXU_s25,NXU_s9,NXU_s41,NXU_s33: std_logic;
signal NXU_s3,NXU_s10,NXU_s42,NXU_s34: std_logic;
signal NXU_s43,NXU_s26,NXU_s39,NXU_s35: std_logic;
signal NXU_s44,NXU_s40,NXU_s4,NXU_s36: std_logic;
signal NXU_s27,NXU_s11,NXU_s18,NXU_s20: std_logic;
signal NXU_s21,NXU_s19,NXU_s12,NXU_s5: std_logic;
signal NXU_s48: std_logic;
signal NXU_s22: std_logic;
signal NXU_s47: std_logic;
signal NXU_s6: std_logic;
signal NXU_s46: std_logic;
signal NXU_s13: std_logic;
signal NXU_s45: std_logic;
signal NXU_s28: std_logic;
signal NXU_s87: std_logic;
signal NXU_s88: std_logic;
signal NXU_s89: std_logic;
signal NXU_s90: std_logic;
signal NXU_s91: std_logic;
signal NXU_s92: std_logic;
signal NXU_s93: std_logic;
signal NXU_s94: std_logic;
signal NXU_s58: std_logic;
signal NXU_s49: std_logic;
signal NXU_s50: std_logic;
signal NXU_s51: std_logic;
signal NXU_s52: std_logic;
signal NXU_s53: std_logic;
signal NXU_s54: std_logic;
signal NXU_s55: std_logic;
signal NXU_s56: std_logic;
signal NXU_s57: std_logic;
begin
NXU_s48<=NXUin_19_A0;
NXU_s47<=NXUin_20_A1;
NXU_s46<=NXUin_21_A2;
NXU_s45<=NXUin_22_A3;
NXUmap1: nandgate4_4_1 port map(in_1 => NXU_s23,in_2 => NXU_s7,in_3 => NXU_s14,in_4 => NXU_s29,out_1 => NXU_s58);
NXUmap2: nandgate4_4_1 port map(in_1 => NXU_s1,in_2 => NXU_s8,in_3 => NXU_s15,in_4 => NXU_s30,out_1 => NXU_s49);
NXUmap3: nandgate4_4_1 port map(in_1 => NXU_s24,in_2 => NXU_s37,in_3 => NXU_s16,in_4 => NXU_s31,out_1 => NXU_s50);
NXUmap4: nandgate4_4_1 port map(in_1 => NXU_s2,in_2 => NXU_s38,in_3 => NXU_s17,in_4 => NXU_s32,out_1 => NXU_s51);
NXUmap5: nandgate4_4_1 port map(in_1 => NXU_s25,in_2 => NXU_s9,in_3 => NXU_s41,in_4 => NXU_s33,out_1 => NXU_s52);
NXUmap6: nandgate4_4_1 port map(in_1 => NXU_s3,in_2 => NXU_s10,in_3 => NXU_s42,in_4 => NXU_s34,out_1 => NXU_s53);
NXUmap7: nandgate4_4_1 port map(in_1 => NXU_s43,in_2 => NXU_s26,in_3 => NXU_s39,in_4 => NXU_s35,out_1 => NXU_s54);
NXUmap8: nandgate4_4_1 port map(in_1 => NXU_s44,in_2 => NXU_s40,in_3 => NXU_s4,in_4 => NXU_s36,out_1 => NXU_s55);
NXUmap9: nandgate4_4_1 port map(in_1 => NXU_s27,in_2 => NXU_s11,in_3 => NXU_s18,in_4 => NXU_s20,out_1 => NXU_s56);
NXUmap10: nandgate4_4_1 port map(in_1 => NXU_s21,in_2 => NXU_s19,in_3 => NXU_s12,in_4 => NXU_s5,out_1 => NXU_s57);
NXUmap11: notgate_1_1 port map(in_1 => NXU_s48,out_1 => NXU_s91);
NXUmap12: notgate_1_1 port map(in_1 => NXU_s22,out_1 => NXU_s87);
NXUmap13: notgate_1_1 port map(in_1 => NXU_s47,out_1 => NXU_s88);
NXUmap14: notgate_1_1 port map(in_1 => NXU_s6,out_1 => NXU_s93);
NXUmap15: notgate_1_1 port map(in_1 => NXU_s46,out_1 => NXU_s89);
NXUmap16: notgate_1_1 port map(in_1 => NXU_s13,out_1 => NXU_s94);
NXUmap17: notgate_1_1 port map(in_1 => NXU_s45,out_1 => NXU_s92);
NXUmap18: notgate_1_1 port map(in_1 => NXU_s28,out_1 => NXU_s90);
NXUmap19: SPLIT_f_ZK_1_5 port map(in_1 => NXU_s87,out_1 => NXU_s1,out_2 => NXU_s2,out_3 => NXU_s3,out_4 => NXU_s4,out_5 => NXU_s5);
NXUmap20: SPLIT_f_ZK_1_7 port map(in_1 => NXU_s88,out_1 => NXU_s6,out_2 => NXU_s7,out_3 => NXU_s8,out_4 => NXU_s9,out_5 => NXU_s10,out_6 => NXU_s11,out_7 => NXU_s12);
NXUmap21: SPLIT_f_ZK_1_7 port map(in_1 => NXU_s89,out_1 => NXU_s13,out_2 => NXU_s14,out_3 => NXU_s15,out_4 => NXU_s16,out_5 => NXU_s17,out_6 => NXU_s18,out_7 => NXU_s19);
NXUmap22: SPLIT_f_ZK_1_2 port map(in_1 => NXU_s90,out_1 => NXU_s20,out_2 => NXU_s21);
NXUmap23: SPLIT_f_ZK_1_6 port map(in_1 => NXU_s91,out_1 => NXU_s22,out_2 => NXU_s23,out_3 => NXU_s24,out_4 => NXU_s25,out_5 => NXU_s26,out_6 => NXU_s27);
NXUmap24: SPLIT_f_ZK_1_9 port map(in_1 => NXU_s92,out_1 => NXU_s28,out_2 => NXU_s29,out_3 => NXU_s30,out_4 => NXU_s31,out_5 => NXU_s32,out_6 => NXU_s33,out_7 => NXU_s34,out_8 => NXU_s35,out_9 => NXU_s36);
NXUmap25: SPLIT_f_ZK_1_4 port map(in_1 => NXU_s93,out_1 => NXU_s37,out_2 => NXU_s38,out_3 => NXU_s39,out_4 => NXU_s40);
NXUmap26: SPLIT_f_ZK_1_4 port map(in_1 => NXU_s94,out_1 => NXU_s41,out_2 => NXU_s42,out_3 => NXU_s43,out_4 => NXU_s44);
NXUout_23_Y_0<=NXU_s58;
NXUout_24_Y_1<=NXU_s49;
NXUout_25_Y_2<=NXU_s50;
NXUout_26_Y_3<=NXU_s51;
NXUout_27_Y_4<=NXU_s52;
NXUout_28_Y_5<=NXU_s53;
NXUout_29_Y_6<=NXU_s54;
NXUout_30_Y_7<=NXU_s55;
NXUout_31_Y_8<=NXU_s56;
NXUout_32_Y_9<=NXU_s57;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
