
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity comparatornxu is 
 port( in_1: in std_logic; --a
       in_2: in std_logic;
       in_3: in std_logic;
       in_4: in std_logic;

       in_5: in std_logic; --b
       in_6: in std_logic;
       in_7: in std_logic;
       in_8: in std_logic;

       out_1: out std_logic; --y1
       out_2: out std_logic; --y2
       out_3: out std_logic --y3
     );
end entity comparatornxu;

architecture one of comparatornxu is

 component comparator 
        port(a,b:in std_logic_vector(3 downto 0); 
               y1,y2,y3:out std_logic);
 end component;

 signal nxu_in1,nxu_in2 :  std_logic_vector(0 to 3);  
 --signal nxu_out1:  std_logic_vector(0 to 2); 
 begin
  nxu_in1 <= in_1&in_2&in_3&in_4;
  nxu_in2 <= in_5&in_6&in_7&in_8;
  d138map: comparator port map(a=>nxu_in1,b=>nxu_in2,y1=>out_1,y2=>out_2,y3=>out_3);

end architecture one;

--******************************************************
 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
--******************************************************
