library IEEE;
use ieee.std_logic_1164.ALL;
--  A testbench has no ports.
entity encoderbtod_tb is
end encoderbtod_tb;
 
architecture behav of encoderbtod_tb is
--  Declaration of the component that will be instantiated.
component encoderbtod
port(
NXUin_19_A0: in std_logic;
NXUin_20_A1: in std_logic;
NXUin_21_A2: in std_logic;
NXUin_22_A3: in std_logic;
NXUout_23_Y_0: out std_logic;
NXUout_24_Y_1: out std_logic;
NXUout_25_Y_2: out std_logic;
NXUout_26_Y_3: out std_logic;
NXUout_27_Y_4: out std_logic;
NXUout_28_Y_5: out std_logic;
NXUout_29_Y_6: out std_logic;
NXUout_30_Y_7: out std_logic;
NXUout_31_Y_8: out std_logic;
NXUout_32_Y_9: out std_logic);
end component;
--  Specifies which entity is bound with the component.
for encoderbtod_0: encoderbtod use entity work.encoderbtod;
signal tb_NXUin_1,tb_NXUin_2,tb_NXUin_3,tb_NXUin_4,NXUout_23_Y_0,NXUout_24_Y_1,NXUout_25_Y_2,NXUout_26_Y_3,NXUout_27_Y_4,NXUout_28_Y_5,NXUout_29_Y_6,NXUout_30_Y_7,NXUout_31_Y_8,NXUout_32_Y_9: std_logic;
begin
--  Component instantiation.
encoderbtod_0: encoderbtod port map (NXUin_19_A0 => tb_NXUin_1,NXUin_20_A1 => tb_NXUin_2,NXUin_21_A2 => tb_NXUin_3,NXUin_22_A3 => tb_NXUin_4,NXUout_23_Y_0 => NXUout_23_Y_0,NXUout_24_Y_1 => NXUout_24_Y_1,NXUout_25_Y_2 => NXUout_25_Y_2,NXUout_26_Y_3 => NXUout_26_Y_3,NXUout_27_Y_4 => NXUout_27_Y_4,NXUout_28_Y_5 => NXUout_28_Y_5,NXUout_29_Y_6 => NXUout_29_Y_6,NXUout_30_Y_7 => NXUout_30_Y_7,NXUout_31_Y_8 => NXUout_31_Y_8,NXUout_32_Y_9 => NXUout_32_Y_9);
 --  This process does the real job.
process
type pattern_type is record
--  The inputsThe expected outputs.
tb_NXUin_1,tb_NXUin_2,tb_NXUin_3,tb_NXUin_4: std_logic;
end record;
--  The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
begin
--  Check each pattern.
for i in patterns'range loop
--  Set the inputs.
tb_NXUin_1 <= patterns(i).tb_NXUin_1;
tb_NXUin_2 <= patterns(i).tb_NXUin_2;
tb_NXUin_3 <= patterns(i).tb_NXUin_3;
tb_NXUin_4 <= patterns(i).tb_NXUin_4;
--  Wait for the results.
wait for 1 ns;
end loop;
wait;
end process;
end behav;
