
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
 
entity pencodernxu is 
  port(in_1: in std_logic;
       in_2: in std_logic;
       in_3: in std_logic;
       in_4: in std_logic;
       in_5: in std_logic;
       in_6: in std_logic;
       in_7: in std_logic;
       in_8: in std_logic;
       out_1: out std_logic;
       out_2: out std_logic;
       out_3: out std_logic);
end entity pencodernxu;

architecture one of pencodernxu is
   component pencoder 
   port( inputp : in std_logic_vector(7 downto 0);
             y : out std_logic_vector(2 downto 0));
   end component;

 signal pencDIn: std_logic_vector(7 downto 0);
 signal pencDOu: std_logic_vector(2 downto 0);

begin
 pencDIn <= in_1&in_2&in_3&in_4&in_5&in_6&in_7&in_8;
 pecmap: pencoder port map(inputp => pencDIn,y => pencDOu);

 out_1 <= pencDOu(0);
 out_2 <= pencDOu(1);
 out_3 <= pencDOu(2);

end architecture one;
 
--u1=inputp0 ---u8=inputp7  y1=output0----y3=output2
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 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
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