
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity half_adder is 
   port(a,b  : in std_logic;
        s,co : out std_logic);
end entity half_adder;
architecture half of half_adder is
 signal c,d: std_logic;
 begin
   c<=a or b;
   d<=a nand b;
   co<= not d;
   s<=c and d;
end half;

--//u1=a ---u2=b  y1=s  y2=co

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