
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity adder8nxu is 
 port( in_1: in std_logic;
       in_2: in std_logic;
       in_3: in std_logic;
       in_4: in std_logic;
       in_5: in std_logic;
       in_6: in std_logic;
       in_7: in std_logic;
       in_8: in std_logic;
       in_9: in std_logic;
       in_10: in std_logic;
       in_11: in std_logic;
       in_12: in std_logic;
       in_13: in std_logic;
       in_14: in std_logic;
       in_15: in std_logic;
       in_16: in std_logic;
       in_17: in std_logic;
       out_1: out std_logic;
       out_2: out std_logic;
       out_3: out std_logic;
       out_4: out std_logic;
       out_5: out std_logic;
       out_6: out std_logic;
       out_7: out std_logic;
       out_8: out std_logic;
       out_9: out std_logic);
end adder8nxu;
architecture one of adder8nxu is
 component adder8 
 port( a,b   : in std_logic_vector(7 downto 0);
        cin  : in std_logic;
        cout : out std_logic;
         sum : out std_logic_vector(7 downto 0));
 end component;
 signal nxu_in1,nxu_in2 :  std_logic_vector(7 downto 0);  
 signal nxu_out1 :  std_logic_vector(7 downto 0); 
 begin
  nxu_in1 <= in_1&in_2&in_3&in_4&in_5&in_6&in_7&in_8;
  nxu_in2 <= in_9&in_10&in_11&in_12&in_13&in_14&in_15&in_16;
  muxmap: adder8 port map(a=>nxu_in1,b=>nxu_in2,cin=>in_17,
                          sum=>nxu_out1,cout=>out_9);
  out_1 <= nxu_out1(7);
  out_2 <= nxu_out1(6); 
  out_3 <= nxu_out1(5);
  out_4 <= nxu_out1(4);

  out_5 <= nxu_out1(3);
  out_6 <= nxu_out1(2); 
  out_7 <= nxu_out1(1);
  out_8 <= nxu_out1(0);
end one;

--u(1)-u(8) a;u(9)-u(16) b; u(17) carry
--y(1)-y(8) sum y9=cout

--******************************************************
 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
--******************************************************
