
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity muxkczd4nxu is 
 port( in_1: in std_logic;
       in_2: in std_logic;
       in_3: in std_logic;
       in_4: in std_logic;
       in_5: in std_logic;
       in_6: in std_logic;
       out_1: out std_logic);
end entity muxkczd4nxu;
architecture one of muxkczd4nxu is
 component muxkczd4 
 port( inputp : in std_logic_vector(3 downto 0);
        a,b  : in std_logic;
           y : out std_logic);
 end component;
 begin
  muxmap: muxkczd4 port map(inputp(3)=>in_1,inputp(2)=>in_2,
                            inputp(1)=>in_3,inputp(0)=>in_4,
                            a=>in_5,b=>in_6,y=>out_1);      
end architecture one;

 --u1=input0 ---u8=input7  y1=output0----y3=output2

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