library IEEE;
use ieee.std_logic_1164.ALL;
--  A testbench has no ports.
entity fulladder_tb is
end fulladder_tb;
 
architecture behav of fulladder_tb is
--  Declaration of the component that will be instantiated.
component fulladder
port(
NXUin_12_CI: in std_logic;
NXUin_13_B: in std_logic;
NXUin_14_A: in std_logic;
NXUout_15_CO: out std_logic;
NXUout_16_SUM: out std_logic);
end component;
--  Specifies which entity is bound with the component.
for fulladder_0: fulladder use entity work.fulladder;
signal tb_NXUin_1,tb_NXUin_2,tb_NXUin_3,NXUout_15_CO,NXUout_16_SUM: std_logic;
begin
--  Component instantiation.
fulladder_0: fulladder port map (NXUin_12_CI => tb_NXUin_1,NXUin_13_B => tb_NXUin_2,NXUin_14_A => tb_NXUin_3,NXUout_15_CO => NXUout_15_CO,NXUout_16_SUM => NXUout_16_SUM);
 --  This process does the real job.
process
type pattern_type is record
--  The inputsThe expected outputs.
tb_NXUin_1,tb_NXUin_2,tb_NXUin_3: std_logic;
end record;
--  The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
begin
--  Check each pattern.
for i in patterns'range loop
--  Set the inputs.
tb_NXUin_1 <= patterns(i).tb_NXUin_1;
tb_NXUin_2 <= patterns(i).tb_NXUin_2;
tb_NXUin_3 <= patterns(i).tb_NXUin_3;
--  Wait for the results.
wait for 1 ns;
end loop;
wait;
end process;
end behav;
