
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity shiftL74 is 
 port( clk : in std_logic;
       a: in std_logic_vector(7 downto 0);
       y: out std_logic_vector(7 downto 0));
end entity shiftL74;

architecture one of shiftL74 is
 begin
  process(clk)
    variable reg8 : std_logic_vector(7 downto 0);
        begin
           if clk'event and clk='1' then
               reg8(6 downto 0):= a(7 downto 1);
               reg8(7):='0';
           else
               reg8 := reg8;    
           end if;
            y<=reg8;
  end process;
end one;
  -- from high to low bit 
  -- out bit

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 --Copyright NXU AGL (2004-2007)
 
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