
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity shiftL74nxu is 
 port( in_1: in std_logic;
       in_2: in std_logic;
       in_3: in std_logic;
       in_4: in std_logic;
       in_5: in std_logic;
       in_6: in std_logic;
       in_7: in std_logic;
       in_8: in std_logic;
       in_9: in std_logic;
       out_1: out std_logic;
       out_2: out std_logic;
       out_3: out std_logic;
       out_4: out std_logic;
       out_5: out std_logic;
       out_6: out std_logic;
       out_7: out std_logic;
       out_8: out std_logic);
end entity shiftL74nxu;
architecture krtl of shiftL74nxu is
component shiftL74 is
 port( clk : in std_logic;
       a: in std_logic_vector(7 downto 0);
       y: out std_logic_vector(7 downto 0));
 end component;
 signal nxu_in1 :  std_logic_vector(7 downto 0);  
 signal nxu_out1 :  std_logic_vector(7 downto 0); 
 begin
  nxu_in1 <= in_2&in_3&in_4&in_5&in_6&in_7&in_8&in_9;
  ship: shiftL74 port map(clk=>in_1,a=>nxu_in1,y=>nxu_out1);
  out_1 <= nxu_out1(7);
  out_2 <= nxu_out1(6); 
  out_3 <= nxu_out1(5);
  out_4 <= nxu_out1(4);

  out_5 <= nxu_out1(3);
  out_6 <= nxu_out1(2); 
  out_7 <= nxu_out1(1);
  out_8 <= nxu_out1(0);
end krtl;

  --//from high to low std_logic 
  --// out std_logic

--******************************************************
 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
--******************************************************

