
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity shiftR75 is 
 port( clk : in std_logic;
       a: in std_logic_vector(7 downto 0);
       y: out std_logic_vector(7 downto 0));
end entity shiftR75;

architecture one of shiftR75 is
 begin
  process(clk)
    variable reg8 : std_logic_vector(7 downto 0);
        begin
           if clk'event and clk='1' then
               reg8(7 downto 1):= a(6 downto 0);
               reg8(0):='0';
           else
               reg8 := reg8;    
           end if;
            y<=reg8;
  end process;
end one;
  --//from high to low bit 
  --// out bit
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