library ieee;
use ieee.std_logic_1164.all;

entity mux21a is 
 port( in_1: in bit;
       in_2: in bit;
       in_3: in bit;
       out_1: out bit);
end entity mux21a;
architecture one of mux21a is
 begin
   out_1<=in_1 when in_3='0' else
       in_2;
end architecture one;

--******************************************************
  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net
 
--******************************************************
