library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_signed.all;
entity decoder74138 is 
 port( g1,g2,g3: in std_logic;
         datain: in std_logic_vector(2 downto 0);
         y: out std_logic_vector(7 downto 0));
end decoder74138;
architecture one of decoder74138 is

 begin
 kcpp: process(g1,g2,g3)
   variable outda: std_logic_vector(7 downto 0);
   begin
    if g1='0' then
      y<="11111111";
    elsif g2='1' then
      y<="11111111";
    elsif g3='1' then
      y<="11111111";
    else
      case datain is
          when "000" => outda:="01111111";
          when "001" => outda:="10111111";      
          when "010" => outda:="11011111";
          when "011" => outda:="11101111";                   
          when "100" => outda:="11110111";
          when "101" => outda:="11111011";      
          when "110" => outda:="11111101";
          when "111" => outda:="11111110"; 
          when others => outda:="00000000";
      end case;
      y<=outda;
end if;
end process kcpp;
end one;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
