
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity adder8 is 
  port(a,b   : in std_logic_vector(7 downto 0);
        cin  : in std_logic;
        cout : out std_logic;
         sum : out std_logic_vector(7 downto 0));
end adder8;
architecture rtl of adder8 is
  signal tmp:std_logic_vector(7 downto 0);
  begin

    process(a,b,cin)
	 begin
       tmp<=a+b+cin;
	   if tmp>255 then
	      cout<='1';		 
       else
	      cout<='0';
	   end if;      
   end process;
   sum<=tmp;               
end rtl;

--u(1)-u(8) a;u(9)-u(16) b; u(17) carry
--y(1)-y(8) sum y9=cout
--put this before process or after process

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 --Copyright NXU AGL (2004-2007)
 
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