
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
 
entity pencoder is 
  port(inputp : in std_logic_vector(7 downto 0);
            y : out std_logic_vector(2 downto 0));
end entity pencoder;

architecture rtl of pencoder is
  begin
   process(inputp)
   begin
   if (inputp(0)='0') then
      y<="111";
   elsif (inputp(1)='0') then
      y<="110";
   elsif (inputp(2)='0') then
      y<="101";
   elsif (inputp(3)='0') then
      y<="100";
   elsif (inputp(4)='0') then
      y<="011";
   elsif (inputp(5)='0') then
      y<="010";
   elsif (inputp(6)='0') then
      y<="001";
   else 
      y<="000";
   end if;
  end process;
end rtl;
 
--u1=inputp0 ---u8=inputp7  y1=output0----y3=output2
 
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