
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity half_addernxu is 
 port( in_1: in std_logic;
       in_2: in std_logic;
       out_1: out std_logic;
       out_2: out std_logic);
end entity half_addernxu;

architecture one of half_addernxu is

 component half_adder 
   port(a,b  : in std_logic;
        s,co : out std_logic);
 end component;

 begin
  addermap: half_adder port map(a=>in_1,b=>in_2,
                                s=>out_1,co=>out_2);
end architecture one;

--u1=a ---u2=b  y1=s  y2=co

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