
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity muxkczd4 is 
 port( inputp : in std_logic_vector(3 downto 0);
        a,b  : in std_logic;
           y : out std_logic);
end entity muxkczd4;
architecture rtl of muxkczd4 is
 signal sel: std_logic_vector(1 downto 0);
 begin
   sel<=a&b;
   process(inputp,sel)
    begin
     if (sel="00") then
        y<=inputp(0);
     elsif (sel="01") then
        y<=inputp(1);
     elsif (sel="10") then
        y<=inputp(2);
     else 
        y<=inputp(3);
     end if;
   end process;
end rtl;

--u1=input0 ---u4=input3  u5=a u6=b   y1=output

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