
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity xianfulb is 
  port( a,b,c: in std_logic_vector(7 downto 0);
          y: out std_logic_vector(7 downto 0));
end xianfulb;
architecture one of xianfulb is
  begin
    p1: process(a,b,c)
     begin
      if ((a>b)and(b>c)) then
         y<=b;
      else
         y<="00000000";
      end if;
    end process p1;
end one;
 
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