 
library IEEE;
use ieee.std_logic_1164.ALL;
entity D_trigger_2_1 is
port(
in_1: in std_logic;
in_2: in std_logic;
out_1: out std_logic);
end D_trigger_2_1;
architecture NXU_beh of D_trigger_2_1 is
signal indata: std_logic_vector(1 downto 0);
begin
p1: process(in_1) is
variable outD: std_logic;
begin
indata <= in_2&outD;
if in_1'event and in_1='1' then
case indata is
when "00" => outD :='0';
when "01" => outD :='0';
when "10" => outD :='1';
when "11" => outD :='1';
when others=>
outD :='0';
end case;
out_1 <= outD;
end if;
end process p1;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
