 
 
  module parityC(pa_in,even_odd,data_in,pa_out,error);

  input pa_in;     //pa_in-->parity check bit 
  input even_odd;  //even_odd--> check way control bit

  input [7:0] data_in;   //input data

  output pa_out;   //pa_out-->out the check rezult  
  output error;    //error--> delicate right or wrong


  wire [7:0] data_in;
  wire pa_in,even_odd;
  wire pa_out,error;

parameter   DELAY=1;
assign #DELAY pa_out=even_odd?^data_in[7:0]:~^data_in[7:0];
assign #DELAY error=even_odd?^{data_in[7:0],pa_in}:~^{data_in[7:0],pa_in};
 
 endmodule
  
//******************************************************
 //Copyright NXU AGL (2004-2007)
 
 //Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 //http://scicoshdl.sourceforge.net
 
//******************************************************
