
 module hamdec(ham_in,data_in,data_out,errork);
 
   input [3:0] ham_in;    // correct code
   input [7:0] data_in;   //input data
 
   output errork;        //error--> delicate right or wrong
   output [7:0] data_out;   //input data
 
   wire [7:0] ham_in,data_in;
   wire pa_in,even_odd;
   reg  [7:0] data_out;
   reg  errork;
 
   parameter   DELAY=1;
   wire [3:0] temp;
 
   assign #DELAY temp[0]=ham_in[3] ^ data_in[7] ^ data_in[6] ^ data_in[4] ^
 data_in[3] ^ data_in[1];
   assign #DELAY temp[1]=ham_in[2] ^ data_in[7] ^ data_in[5] ^ data_in[4] ^ 
data_in[2] ^ data_in[1];
   assign #DELAY temp[2]=ham_in[1] ^ data_in[6] ^ data_in[5] ^ data_in[4] ^
 data_in[0];
   assign #DELAY temp[3]=ham_in[0] ^ data_in[3] ^ data_in[2] ^ data_in[1] ^
 data_in[0];
 
   always@(data_in)
    begin
       data_out=data_in;
       case(temp)
 
           4'h0:begin
                  errork=0;
                end  
           4'h1:begin
                  errork=1;
                end  
           4'h2:begin
                  errork=1;
                end  
           4'h4:begin
                  errork=1;
                end  
           4'h8:begin
                  errork=1;
                end  
           4'h3:begin
                  errork=1;
                  data_out[7]=~data_in[7];
                end 
           4'h5:begin
                  errork=1;
                  data_out[6]=~data_in[6];
                end  
           4'h6:begin
                  errork=1;
                  data_out[5]=~data_in[5];
                end  
           4'h7:begin
                  errork=1;
                  data_out[4]=~data_in[4];
                end  
           4'h9:begin
                  errork=1;
                  data_out[3]=~data_in[5];
                end  
           4'ha:begin
                  errork=1;
                  data_out[2]=~data_in[2];
                end  
           4'hb:begin
                  errork=1;
                  data_out[1]=~data_in[1];
                end  
           4'hc:begin
                  errork=1;
                  data_out[0]=~data_in[0];
                end 
     endcase
    end 
  endmodule
   
//******************************************************
 //Copyright NXU AGL (2004-2007)
 
 //Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 //http://scicoshdl.sourceforge.net
 
//******************************************************

