
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;

entity demuxBUS_2 is
  port(s1: in std_logic;
       data1 : in std_logic_vector(7 downto 0);
       data2 : in std_logic_vector(7 downto 0);
         y1 : out std_logic_vector(7 downto 0));
  end demuxBUS_2;

architecture demux2 of demuxBUS_2 is
  begin
  p1: process(s1,data1,data2)
   begin
     if s1='1' then
        y1<=data1;
     else
        y1<=data2;
     end if;    
  end process p1;
end demux2;

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