 
`include "fulladder.v"
`timescale 1ns/1ns
module fulladder_tb(tb_in_1,tb_in_2,tb_in_3,tb_out_1,tb_out_2);
input tb_in_1,tb_in_2,tb_in_3;
output tb_out_1,tb_out_2;
fulladder testB (.NXUin_1_CI(tb_in_1),.NXUin_2_B(tb_in_2),.NXUin_3_A(tb_in_3),
.NXUout_1_CO(tb_out_1),.NXUout_2_SUM(tb_out_2));
endmodule
 

 //******************************************************
  //verilog compiler

  //ZhangDong&KangCai (2004-2008)
 
  //http://scicoshdl.sourceforge.net

 //******************************************************

