library ieee;
use ieee.std_logic_1164.all;

entity COMP2a is 
 port( in_1: in bit;
       in_2: in bit;
       out_1: out bit);
end entity COMP2a;
architecture one of COMP2a is
 begin
   process(in_1,in_2)
      begin
       if in_1 > in_2 then out_1<= '1';
       else out_1<= '0';
       end if;
   end process;     
end architecture one;

--******************************************************
  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net
 
--******************************************************
