 
library IEEE;
use ieee.std_logic_1164.ALL;
entity shift_rg is
port(
NXUin_5_D: in std_logic;
NXUin_6_CP: in std_logic;
NXUout_7_S_out: out std_logic;
NXUout_8_P_Q0: out std_logic;
NXUout_9_P_Q1: out std_logic;
NXUout_10_P_Q2: out std_logic;
NXUout_11_P_Q3: out std_logic);
end shift_rg;
architecture NXU_beh of shift_rg is
component D_trigger_2_1
port(
in_1,in_2: in std_logic;
out_1: out std_logic);
end component;
component SPLIT_f_ZK_1_4
port(
in_1: in std_logic;
out_1,out_2,out_3,out_4: out std_logic);
end component;
component SPLIT_f_ZK_1_2
port(
in_1: in std_logic;
out_1,out_2: out std_logic);
end component;
signal NXU_s1,NXU_s13: std_logic;
signal NXU_s4,NXU_s11: std_logic;
signal NXU_s3,NXU_s9: std_logic;
signal NXU_s2,NXU_s7: std_logic;
signal NXU_s28: std_logic;
signal NXU_s29: std_logic;
signal NXU_s30: std_logic;
signal NXU_s31: std_logic;
signal NXU_s32: std_logic;
signal NXU_s5: std_logic;
signal NXU_s12: std_logic;
signal NXU_s10: std_logic;
signal NXU_s8: std_logic;
signal NXU_s6: std_logic;
begin
NXU_s13<=NXUin_5_D;
NXU_s28<=NXUin_6_CP;
NXUmap1: D_trigger_2_1 port map(in_1 => NXU_s1,in_2 => NXU_s13,out_1 => NXU_s32);
NXUmap2: D_trigger_2_1 port map(in_1 => NXU_s4,in_2 => NXU_s11,out_1 => NXU_s31);
NXUmap3: D_trigger_2_1 port map(in_1 => NXU_s3,in_2 => NXU_s9,out_1 => NXU_s30);
NXUmap4: D_trigger_2_1 port map(in_1 => NXU_s2,in_2 => NXU_s7,out_1 => NXU_s29);
NXUmap5: SPLIT_f_ZK_1_4 port map(in_1 => NXU_s28,out_1 => NXU_s1,out_2 => NXU_s2,out_3 => NXU_s3,out_4 => NXU_s4);
NXUmap6: SPLIT_f_ZK_1_2 port map(in_1 => NXU_s29,out_1 => NXU_s5,out_2 => NXU_s6);
NXUmap7: SPLIT_f_ZK_1_2 port map(in_1 => NXU_s30,out_1 => NXU_s7,out_2 => NXU_s8);
NXUmap8: SPLIT_f_ZK_1_2 port map(in_1 => NXU_s31,out_1 => NXU_s9,out_2 => NXU_s10);
NXUmap9: SPLIT_f_ZK_1_2 port map(in_1 => NXU_s32,out_1 => NXU_s11,out_2 => NXU_s12);
NXUout_7_S_out<=NXU_s5;
NXUout_8_P_Q0<=NXU_s12;
NXUout_9_P_Q1<=NXU_s10;
NXUout_10_P_Q2<=NXU_s8;
NXUout_11_P_Q3<=NXU_s6;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
