 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity hamgennxu is 
 
  port( in_1: in std_logic;
        in_2: in std_logic;
        in_3: in std_logic;
        in_4: in std_logic;
        in_5: in std_logic;
        in_6: in std_logic;
        in_7: in std_logic;
        in_8: in std_logic;
           --out1 data high
        out_1 : out std_logic;          
        out_2 : out std_logic;
        out_3 : out std_logic;
        out_4 : out std_logic 
      );
end hamgennxu;
 
architecture one of hamgennxu is

  component hamgen 
   port(data_in: in std_logic_vector(7 downto 0);
        ham_out: out std_logic_vector(3 downto 0));
  end component;
 
  signal nxu_in1 :  std_logic_vector(7 downto 0); 
  signal nxu_out1 :  std_logic_vector(3 downto 0);  
 
begin
  nxu_in1 <= in_1&in_2&in_3&in_4&in_5&in_6&in_7&in_8;
 
  hgmap: hamgen port map(data_in=>nxu_in1,ham_out=>nxu_out1);
 
  out_1 <= nxu_out1(3);         
  out_2 <= nxu_out1(2); 
  out_3 <= nxu_out1(1); 
  out_4 <= nxu_out1(0); 

end  one;
 
 
--******************************************************
 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
--******************************************************
