 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_signed.all;
 entity fanma877 is 
  port( a: in std_logic_vector(0 to 7);
        y: out std_logic_vector(0 to 7));
 end entity fanma877;
 architecture one of fanma877 is
 
  begin
   --empd:=a(7);
   process(a)
     variable tempd: std_logic_vector(0 to 7);
     begin
   if a(7) <= '0' then
      y<=a;
   else
     y(7)<='1';
     for i in 0 to 6 loop
       if a(i)='1' then
          y(i)<='0';
       else
          y(i)<='1'; 
       end if;         
     end loop;
   end if;
   end process;
   
 end one;


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