
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity mux21anxu is 
 port( in_1: in bit;
       in_2: in bit;
       in_3: in bit;
       out_1: out bit);
end entity mux21anxu;
architecture one of mux21anxu is
 component mux21a 
   port( a,b: in bit;
         s: in bit;
         y: out bit);
 end component;
begin
 muxmap: mux21a port map(a=>in_1,b=>in_2,s=>in_3,y=>out_1);
end architecture one;


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