
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_signed.all;
 entity juedu79nxu is 
  port( in_1: in std_logic;
        in_2: in std_logic;
        in_3: in std_logic;
        in_4: in std_logic;
        in_5: in std_logic;
        in_6: in std_logic;
        in_7: in std_logic;
        in_8: in std_logic;
        out_1: out std_logic;
        out_2: out std_logic;
        out_3: out std_logic;
        out_4: out std_logic;
        out_5: out std_logic;
        out_6: out std_logic;
        out_7: out std_logic;
        out_8: out std_logic);
 end entity juedu79nxu;

 architecture krtl of juedu79nxu is

  component juedu79 
  port( a: in std_logic_vector(7 downto 0);
        y: out std_logic_vector(7 downto 0));
  end component;

signal juedDIn: std_logic_vector(7 downto 0);
signal juedDOu: std_logic_vector(7 downto 0);

begin

juedDIn <= in_1&in_2&in_3&in_4&in_5&in_6&in_7&in_8;

juedu79p: juedu79 port map(a=>juedDIn,y=>juedDOu);

 out_1 <= juedDOu(7);
 out_2 <= juedDOu(6);
 out_3 <= juedDOu(5);
 out_4 <= juedDOu(4);
 out_5 <= juedDOu(3);
 out_6 <= juedDOu(2);
 out_7 <= juedDOu(1);
 out_8 <= juedDOu(0);

end krtl;

--//u(1)hight bit u2--u8 7  +127  -127
--//y(1)2--y8 7
--******************************************************
 --Copyright NXU AGL (2004-2007)
 
 --Powered by scicos-hdl 0.4 ZhangDong&KangCai 2007 NXU
 
 --http://scicoshdl.sourceforge.net
 
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