
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity kcxflb is 
  port( b: in std_logic_vector(7 downto 0);
        y: out std_logic_vector(7 downto 0));
end kcxflb;
architecture one of kcxflb is
  begin
    p1: process(b)
    begin
      if ("11111111">b)and(b>"00000000") then 
         y<=b;
     else
        y<="00000000";
      end if;
    end process p1;
end one;
 
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