library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity fanma877nxu is 
  port( in_1: in std_logic;
        in_2: in std_logic;
        in_3: in std_logic;
        in_4: in std_logic;
        in_5: in std_logic;
        in_6: in std_logic;
        in_7: in std_logic;
        in_8: in std_logic;
        out_1: out std_logic;
        out_2: out std_logic;
        out_3: out std_logic;
        out_4: out std_logic;
        out_5: out std_logic;
        out_6: out std_logic;
        out_7: out std_logic;
        out_8: out std_logic);
end entity fanma877nxu;

architecture krtl of fanma877nxu is

component fanma877 
  port( a: in std_logic_vector(0 to 7);
        y: out std_logic_vector(0 to 7));
end component;

 signal fanmaDIn: std_logic_vector(0 to 7);
 signal fanmaDOu: std_logic_vector(0 to 7);
 
begin
 
 fanmaDIn <= in_1&in_2&in_3&in_4&in_5&in_6&in_7&in_8;

 fanma79p: fanma877 port map(a=>fanmaDIn,y=>fanmaDOu);

 out_1 <= fanmaDOu(7);
 out_2 <= fanmaDOu(6);
 out_3 <= fanmaDOu(5);
 out_4 <= fanmaDOu(4);
 out_5 <= fanmaDOu(3);
 out_6 <= fanmaDOu(2);
 out_7 <= fanmaDOu(1);
 out_8 <= fanmaDOu(0); 

end krtl;


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