library IEEE;
use ieee.std_logic_1164.ALL;
--  A testbench has no ports.
entity shift_rg_tb is
end shift_rg_tb;
 
architecture behav of shift_rg_tb is
--  Declaration of the component that will be instantiated.
component shift_rg
port(
NXUin_5_D: in std_logic;
NXUin_6_CP: in std_logic;
NXUout_7_S_out: out std_logic;
NXUout_8_P_Q0: out std_logic;
NXUout_9_P_Q1: out std_logic;
NXUout_10_P_Q2: out std_logic;
NXUout_11_P_Q3: out std_logic);
end component;
--  Specifies which entity is bound with the component.
for shift_rg_0: shift_rg use entity work.shift_rg;
signal tb_NXUin_1,tb_NXUin_2,NXUout_7_S_out,NXUout_8_P_Q0,NXUout_9_P_Q1,NXUout_10_P_Q2,NXUout_11_P_Q3: std_logic;
begin
--  Component instantiation.
shift_rg_0: shift_rg port map (NXUin_6_CP => tb_NXUin_1,NXUin_5_D => tb_NXUin_2,NXUout_7_S_out => NXUout_7_S_out,NXUout_8_P_Q0 => NXUout_8_P_Q0,NXUout_9_P_Q1 => NXUout_9_P_Q1,NXUout_10_P_Q2 => NXUout_10_P_Q2,NXUout_11_P_Q3 => NXUout_11_P_Q3);
 --  This process does the real job.
process
type pattern_type is record
--  The inputsThe expected outputs.
tb_NXUin_1,tb_NXUin_2: std_logic;
end record;
--  The patterns to apply.
type pattern_array is array (natural range <>) of pattern_type;
constant patterns : pattern_array :=
begin
--  Check each pattern.
for i in patterns'range loop
--  Set the inputs.
tb_NXUin_1 <= patterns(i).tb_NXUin_1;
tb_NXUin_2 <= patterns(i).tb_NXUin_2;
--  Wait for the results.
wait for 1 ns;
end loop;
wait;
end process;
end behav;
