 
library IEEE;
use ieee.std_logic_1164.ALL;
entity dclrtrig is
port(
NXUin_2_clk: in std_logic;
NXUin_3_clr: in std_logic;
NXUin_4_d: in std_logic;
NXUout_5_q: out std_logic);
end dclrtrig;
architecture NXU_beh of dclrtrig is
component D_trigger_3_1
port(
in_1,in_2,in_3: in std_logic;
out_1: out std_logic);
end component;
signal NXU_s3,NXU_s4,NXU_s5: std_logic;
signal NXU_s9: std_logic;
begin
NXU_s3<=NXUin_2_clk;
NXU_s4<=NXUin_3_clr;
NXU_s5<=NXUin_4_d;
NXUmap1: D_trigger_3_1 port map(in_1 => NXU_s3,in_2 => NXU_s4,in_3 => NXU_s5,out_1 => NXU_s9);
NXUout_5_q<=NXU_s9;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
