
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;

entity muxBUS_3 is
  port(s1: in std_logic;
       s2: in std_logic;
       data : in std_logic_vector(7 downto 0);
         y1 : out std_logic_vector(7 downto 0);
         y2 : out std_logic_vector(7 downto 0);
         y3 : out std_logic_vector(7 downto 0));
end muxBUS_3;

architecture mux3 of muxBUS_3 is
  begin
  p1:process(s1,s2)
    begin
     if ((s1='1')and(s2='1')) then
          y1<=data;
          y2<="00000000";
          y3<="00000000";
     elsif ((s1='1')and(s2='0')) then
          y1<="00000000";
          y2<=data;
          y3<="00000000";
     else
          y1<="00000000";
          y2<="00000000";
          y3<=data;
     end if;
end process p1;
end mux3;

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