 
library IEEE;
use ieee.std_logic_1164.ALL;
entity andgate2_2_1 is
port(
in_1: in std_logic;
in_2: in std_logic;
out_1: out std_logic);
end andgate2_2_1;
architecture NXU_beh of andgate2_2_1 is
begin
p1: process(in_1,in_2)
variable indata: std_logic_vector(1 downto 0);
begin
indata := in_1&in_2;
case indata is
when "00" =>
out_1 <= '0';
when "10" =>
out_1 <= '0';
when "01" =>
out_1 <= '0';
when "11" =>
out_1 <= '1';
when others=>
out_1 <= '0';
end case;
end process p1;
end NXU_beh;

 --******************************************************
  --VHDL compiler

  --ZhangDong&KangCai (2004-2008)
 
  --http://scicoshdl.sourceforge.net

 --******************************************************
