
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mux21a is 
 port( a,b: in bit;
         s: in bit;
         y: out bit);
end entity mux21a;
architecture one of mux21a is
 begin
   y<=a when s='0' else
       b;
end architecture one;

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