Overview
Scicos-HDL integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. Scicos-HDL shortens digital circuit design cycles by helping you create the hardware representation in an modeling-friendly development environment. You can combine existing Scicos blocks with Scicos-HDL blocks and to link system-level design . It is a open source project under Scilab ‘s license, the release vision can help to design and simulate some small-scale digital circuit system with its Hardware Description Language generation. We now will make it as a tool for teaching digital circuit design. Now it supports SystemC, VHDL&Verilog Languages.
Features:
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Links The Scilab/Scicos with the Digital circuit design(EDA).
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Integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation.
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Enables complex signal processing combined with powerful mathematical tools.
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Inside libraries: Sequential logic library, Combinational logic library, Ipcore library, simulation library.
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Support mixed-simulation with the Scicos blocks.
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Automatically generates Description Language(SystemC ,VHDL and Verilog ).
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Automatic propagation of signal names to generated HDL.
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You can specify most values in the block parameter dialog boxes using Scicos workspace.
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Mix-simulation with original Scicos blocks and Scicos-HDL blocks.
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Open interface for users to add blocks.
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Under GPL LICENCE.